This is a laptop processor with integrated graphics, built on a 7nm semiconductor process and operating within a 28W Thermal Design Power rating, placing it in the mid-range mobile performance segment. It supports 64-bit computing and uses PCIe 5.0 for connectivity, with a maximum CPU temperature threshold of 110°C.
Using big.LITTLE technology, the processor arranges its cores into two clusters — four performance cores at 1.7GHz and eight efficiency cores at 1.2GHz — handling 18 threads in total. Under peak demand, it can boost up to a turbo clock of 4.6GHz, supported by an 18MB L3 cache that helps reduce data fetch latency across workloads. The clock multiplier is locked, so frequencies operate strictly within the factory-defined range with no manual tuning available.
Benchmark results place this processor at a PassMark multi-threaded score of 22,418, reflecting its capacity across parallel workloads, while the single-core PassMark result of 3,518 gives a clear indication of per-thread responsiveness for sequentially demanding tasks.
The integrated graphics unit operates at a base clock of 300MHz and boosts up to 2200MHz, with 8 execution units, 1024 shading units, and 32 render output units handling graphical tasks. It supports DirectX 12 Ultimate, OpenGL 4.6, and OpenCL 3, covering both rendering pipelines and general-purpose GPU compute workloads within an integrated mobile graphics configuration.
The processor supports DDR5 memory running at up to 5600MHz across two channels, with a maximum addressable capacity of 96GB. The dual-channel setup helps maintain balanced memory throughput for mobile workloads, though ECC memory is not supported, keeping the platform within consumer rather than data-integrity-critical use cases.
The processor supports multithreading and includes the NX bit for hardware-enforced memory protection. Its instruction set support covers MMX, SSE 4.1, SSE 4.2, AVX, AVX2, FMA3, F16C, and AES, giving well-optimized software the ability to leverage vectorized arithmetic, half-precision floating-point conversion, and hardware-accelerated encryption at the silicon level.