The Intel Core Ultra 7 265 is a desktop processor built for the LGA 1851 socket, with compatibility limited to Z890 chipset motherboards. It is manufactured on a 3 nm process node and carries a thermal design power rating of 65W, with a maximum operating temperature of 105 °C. The chip supports 64-bit computing, includes integrated graphics, and interfaces with expansion hardware through PCIe 5.0.
The Core Ultra 7 265 uses big.LITTLE technology to combine eight performance cores running at 2.4 GHz with twelve efficiency cores at 1.8 GHz, yielding 20 threads in total. With a clock multiplier of 24 and Turbo Boost version 2, the processor can reach a turbo clock speed of 5.3 GHz, though the multiplier is locked and cannot be adjusted for overclocking. Cache resources are generous, with 36 MB of L2 cache and 30 MB of L3 cache available to help sustain throughput across varied workloads.
In multi-threaded testing, the Core Ultra 7 265 achieves a PassMark score of 48,917, while its single-threaded PassMark result stands at 4,633. Cinebench R20 results follow a similar pattern, with a multi-core score of 10,181 and a single-core result of 847.
The integrated graphics unit has a base clock of 300 MHz and can reach a turbo frequency of 1950 MHz. It supports up to four displays simultaneously and is compatible with DirectX 12, along with OpenGL 4.5 and OpenCL 3, covering a range of graphics and compute workloads handled directly by the processor.
The Core Ultra 7 265 supports DDR5 memory at speeds up to 6400 MHz across a dual-channel configuration, allowing a maximum installed capacity of 192 GB. ECC memory is also supported, which enables error correction at the hardware level for use cases where data integrity is a priority.
The Core Ultra 7 265 supports a broad set of instruction sets, including MMX, AVX, AVX2, FMA3, F16C, AES, SSE 4.1, and SSE 4.2, covering vectorized math, encryption acceleration, and extended multimedia operations. The processor also includes the NX bit, a hardware-level security feature that helps prevent certain classes of malicious code from executing in memory regions marked as non-executable.